(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a low junction leakage current and, more particularly, to a method suited to manufacturing memory devices such as DRAM and SRAM.
(b) Description of the Related Art
Portable data processing devices such as cellular phone and personal digital assistant are increasingly used in these days. In general, a memory cell in a memory device such as DRAM and SRAM used in the portable data processing devices should have a MOS transistor or MOS transistors having lower junction leakage current. With reference to FIGS. 1A to 1G, a conventional method for manufacturing a DRAM device will be described hereinafter.
A 250-nm-deep trench is formed on a surface region of a silicon substrate 1, followed by depositing a silicon oxide film 2 within the trench to form a shallow trench isolation (STI) structure. Subsequently, a 10-nm-thick silicon oxide film 3 is formed on the silicon substrate 1, as shown in FIG. 1A, followed by implantation of boron ions through the silicon oxide film 3 for three times. The three-time implantation of boron ions is conducted at an acceleration energy of 250 keV and a dosage of 1×1013/cm2, at an acceleration energy of 150 keV and a dosage of 5×1012 cm/2, and at an acceleration energy of 80 keV and a dosage of 3×1012/cm2. Thereafter, a heat treatment is performed at a substrate temperature of 1000 degrees C. for 30 minutes to restore the silicon substrate from the damages caused by boron implantation, thereby forming p-wells 4 on the silicon substrate 1.
Subsequently, further implantation of boron ions through the thin silicon oxide film 3 is performed at an acceleration energy of 15 keV and a dosage of 1×1013/cm2, thereby forming p-type channel regions 6, as shown in FIG. 1B. After removing the thin silicon oxide film 3, a 6-nm-thick gate insulation film 7 made of silicon oxide is formed using a thermal oxidation technique. The threshold voltage of a cell transistor is generally designed by determining the impurity concentration profile of the p-type channel region 6 and the thickness of the gate insulation film 7.
Thereafter, on the gate insulation film 7 are consecutively formed a 100-nm-thick polysilicon film 9a doped with phosphorous at a concentration of 4×1020/cm3, a 70-nm-thick tungsten silicide film 9b, and a 130-nm-thick insulation film 8 including a silicon nitride layer and a silicon oxide layer. Subsequently, the insulation film 8, tungsten silicide film 9b and polysilicon film 9a are patterned to configure 2-layer gate electrodes 9 and overlying insulation films 8. Side-wall oxide films 10 are then formed on the side walls of the gate electrodes 9 by using a thermal oxidation technique. This thermal oxidation also oxidizes surface portions of the silicon substrate 1 exposed by the patterning process.
Thereafter, implantation of phosphorous ions is performed twice through the gate insulation film 7 by a self-aligned process using the gate electrodes 9 as a mask at an acceleration energy of 20 keV and a dosage of 7×1012/cm2, and at an acceleration energy of 15 keV and a dosage of 7×1012/cm2. Another heat treatment is then performed at a substrate temperature of 1000 degrees C. for 10 seconds to activate the implanted phosphorous ions for obtaining source/drain diffused regions 11 as well as to activate dopants in the diffused regions formed in the peripheral area of the memory device, as shown in FIG. 1D.
A silicon nitride film is then deposited and subjected to an etch-back process, thereby forming a 40-nm-thick silicon-nitride side spacers 12, as shown in FIG. 1E. Implantation of phosphorous ions through the gate insulation film 7 and the source/drain diffused regions 11 is then performed by a self-aligned technique using the insulation films 8 and the side spacers 12 on the gate electrodes 9, thereby forming electric-field alleviating regions 13 on the bottoms of the source/drain diffused regions 11.
Subsequently, as shown in FIG. 1F, a silicon oxide film and a silicon nitride film are consecutively deposited on the entire surface, thereby forming a 350-nm-thick interlayer dielectric film 14. The interlayer dielectric film 14 is then etched-back using an anisotropic etching technique for planarization thereof. A patterning process is then performed to the interlayer dielectric film 14, insulation films 8, side spacers 12 and gate insulation film 7 to form through-holes 15a for exposing therethrough surface portions of the source/drain diffused regions 11. Implantation of phosphorous ions is again performed by a self-aligned technique using the interlayer dielectric film 14, insulation films 8 and side spacers 12 as a mask, toward the bottom of the electric-field alleviating regions 13 through the source/drain diffused regions 11. A polysilicon film doped with phosphorous ions at a concentration of 2×1020/cm3 is then deposited on the interlayer dielectric film 14 and in the through-holes 15a, and etched-back to configure 350-nm-long contact plugs 15.
Subsequently, a 50-nm-thick interlayer dielectric film 19 made of silicon oxide is deposited and patterned to form through-holes 17a therein. A 100-nm-thick tungsten film is then deposited on the interlayer dielectric film 19 and in the through-holes 17a, and patterned to configure bit lines 17. Thereafter, an interlayer dielectric film 20 is deposited, followed by patterning the interlayer dielectric films 19 and 20 to form through-holes 21a therein and filling the through-holes 21a with contact plugs 21. Cell capacitors 18 each having a cylindrical structure and including a bottom electrode 22, an insulation film 23 and a top electrode 24 are then formed, the bottom electrode 22 being in contact with the underlying contact plug 21, as shown in FIG. 1G.
The memory cells should be downsized along with the development of the higher-density DRAMs. For meeting this downsizing of the memory cell, the gate length of the MOS transistor must be reduced while maintaining the previous threshold voltage of the MOS transistor. This is generally achieved by increasing the dopant concentration of the channel region 6 of the MOS transistor. In this structure, however, there arises a problem that the electric field across the junction between the channel region 6 and the source/drain diffused regions 11 is intensified to thereby increase the junction leakage current. The increase of the junction leakage current degrades the charge storage capability, or data storage capability, of the memory cell. For reducing the junction leakage current, two technologies are considered: one for alleviating the electric field intensity across the p-n junction; and the other for reducing the number of vacancy type defects or vacancy type defects which are the origin of the junction leakage current.
The technology for alleviating the electric field intensity is generally employed in the conventional technique for preventing the decrease of charge storage capability of the memory cell, and a variety of proposals therefor have been presented. Patent Publication JP-3212150, for example, discloses a technique wherein the profile of the dopant concentrations (or carrier density) in the p- and n-type regions adjacent to the p-n junction are controlled so that the electric field across the p-n junction does not exceed 1 MV/cm, at which the local Zener effect markedly arises in general. However, the technology for alleviating the electric field across the junction, such as proposed in the publication, only achieves a limited effect for the far-downsized memory devices. Thus, the other technology for reducing the number of vacancy type defects now attracts more attentions in the memory device industry.
The vacancy type defects are generally formed in the two-step procedure. First, the step of implanting dopants in the silicon substrate for forming therein the source/drain diffused regions generates implantation damages in the source/drain diffused regions. Although most of the implantation damages are restored by the subsequent heat treatment, some are transformed into vacancy type defects during this heat treatment. The vacancy type defects remain in the vicinities of the metallurgical junctions 25 formed between the source/drain diffused regions 11 and the doped channel region 6, as shown by “x” marks in FIG. 6, due to the influence by the compressive strain generated during the heat treatment. This phenomenon was assured by an experiment using an electrically detected magnetic resonance, as described in a publication “Defects related to DRAM leakage current studied by electrically detected magnetic resonance”, by T. Umeda et al., vol. 308 –310, pp1169 –1172 (2001).
It is known that the vacancy type defect includes divacancy plus one or two oxygen atoms within a lattice structure of the silicon substrate, as shown in FIG. 7. The vacancy type defect is also associated with neighboring dangling bonds 26, which are uncoupled bonds of the silicon atoms. The vacancy type defects remaining in the vicinity of the metallurgical junction 25 are raised to an energy level within the energy bandgap by the presence of the dangling bonds, thereby generating junction leakage current due to this energy level. The junction leakage current reduces the charge storage capability of the memory cell, as described above.
Patent Publication JP-A-1(1989)-32640 describes a technique for reducing the leakage current which may otherwise increase in the vicinity of the dopant diffused region along with a smaller depth thereof. In this publication, by using implantation of fluorine together with a heat treatment, the traps are reduced by the fluorine in the vicinity of the diffused region, to thereby reduce the leakage current in the vicinity of the diffused region.
JP-A-1-32640 is silent to the vacancy type defect remaining in the vicinity of the metallurgical junction formed between the source/drain diffused regions and the doped channel region. In addition, the technique described in this publication does not achieve the suppression of the junction leakage current caused by the vacancy type defect.